Hardware implementation of a low-complexity detector for large MIMO

Large MIMO systems represents an effective way to transmit reliably at very high data-rate, but their complexity still represents a problem for practical realization. This paper addresses the hardware implementation of a low-complexity and high-performance detector for a 32 times 32 MIMO. It allows...

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Bibliographic Details
Published in2009 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 593 - 596
Main Authors Cerato, B., Viterbo, E.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2009
Subjects
Bit error rate
Costs
Detectors
Filters
Hardware
hardware implementation
Large MIMO
Maintenance
MIMO
MIMO detector
Quadrature amplitude modulation
Receiving antennas
Transmitting antennas
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ISBN1424438276
9781424438273
ISSN0271-4302
DOI10.1109/ISCAS.2009.5117818

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Summary:Large MIMO systems represents an effective way to transmit reliably at very high data-rate, but their complexity still represents a problem for practical realization. This paper addresses the hardware implementation of a low-complexity and high-performance detector for a 32 times 32 MIMO. It allows to reach very high data rate, up to more than 170 Mbit/s with a 64 QAM with BER 10 -1.5 -10 -2 and constitutes a cost effective improvement over basic detection schemes.
ISBN:1424438276
9781424438273
ISSN:0271-4302
DOI:10.1109/ISCAS.2009.5117818