Embedded wafer level packages with laterally placed and vertically stacked thin dies

• Published in: 2009 59th Electronic Components and Technology Conference pp. 1537 - 1543
• Main Authors: Sharma, G., Rao, V.S., Kumar, A., Su, N., Lim Ying Ying, Khong Chee Houe, Lim, S., Sekhar, V.N., Rajoo, R., Kripesh, V., Lau, J.H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: Compression molding; Dielectrics; Encapsulation; Packaging; Stacking; Temperature sensors; Testing; Thermal stresses; Thin film inductors; Wafer scale integration
• ISBN: 1424444756; 9781424444755
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2009.5074217

Two embedded micro wafer level packages (EMWLP) with (1) laterally placed and (2) vertically stacked thin dies are designed and developed. 3D stacking of thin dies is illustrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm times 10 mm times 0.4 mm and solder ball pitch of 0.4 mm. As part of the work several key processes like thin die stacking, 8 inch wafer encapsulation using compression molding, low temperature dielectric with processing temperature less than 200 degC have been developed. The developed EMWLP components successfully pass 1000 air to air thermal cycling (-40 to 125degC), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (> 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL and package thicknesses can lead to designs with improved mechanical reliability.