65nm Cu Integration and Interconnect Reliability in Low Stress K=2.75 SiCOH

• Published in: 2006 International Interconnect Technology Conference pp. 9 - 11
• Main Authors: McGahay, V., Bonilla, G., Chen, F., Christiansen, C., Cohen, S., Cullinan-Scholl, M., Demarest, J., Dunn, D., Engel, B., Fitzsimmons, J., Gill, J., Grunow, S., Herbst, B., Hichri, H., Ida, K., Klymko, N., Kiene, M., Labelle, C., Lee, T., Liniger, E., Liu, X.H., Madan, A., Malone, K., Martin, J., McLaughlin, P.V., Minami, P., Molis, S., Muzzy, C., Nguyen, S., Patel, J.C., Restaino, D., Sakamoto, A., Shaw, T.M., Shimooka, Y., Shobha, H., Simonyi, E., Widodo, J., Grill, A., Hannon, R., Lane, M., Nye, H., Spooner, T., Wisnieff, R., Ivers, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2006
• Subjects: Assembly; Dielectric materials; Electronic components; Electronic packaging thermal management; Optical films; Research and development; Semiconductor device manufacture; Semiconductor device packaging; Tensile stress; Thermal engineering
• ISBN: 1424401046; 9781424401048
• ISSN: 2380-632X; 2380-6338
• DOI: 10.1109/IITC.2006.1648631

A low tensile stress SiCOH dielectric with K=2.15 has been developed for implementation in the 2times and 4times fatwire levels for enhanced RC performance in the 65nm technology node. Integration challenges related to mechanical integrity and process-induced damage were successfully overcome. Yield and interconnect reliability metrics comparable to dense K=3 SiCOH have been achieved. Package deep thermal cycle showed sensitivity to assembly which is controllable though chip edge structural engineering