Design for reliability in via middle and via last 3-D chipstacks incorporating TSVs

Two test chips have been designed to determine the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). One of the chips uses via-middle technology while the other uses via-last technology. Both chips are fabricated in a commercial foundry using a 65 nm CMOS process...

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Bibliographic Details
Published in2010 12th Electronics Packaging Technology Conference pp. 328 - 332
Main Authors Trigg, A.D., Hong Yu, Li, Zhong Xiong, Yong, Jing Lin, Shi, Cheng Kuo, Cheng, Khan, Navas, Keng Hwa, Teo, Shan, Gao
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2010
Subjects
Copper
Delamination
Reliability
Silicon
Stress
Through-silicon vias
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Summary:Two test chips have been designed to determine the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). One of the chips uses via-middle technology while the other uses via-last technology. Both chips are fabricated in a commercial foundry using a 65 nm CMOS process. Both chips contain test structures designed to measure performance of transistors and other active devices, the resistance and electromigration performance of TSVs and microbumps, thermal performance, corrosion related to moisture ingress. This paper will focus on the reliability features of the chips, excluding the active devices.
ISBN:9781424485604
1424485606
DOI:10.1109/EPTC.2010.5702657