A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET

A 13bit 5GS/s time-interleaved ADC is described which uses a chopping technique to reduce the effect of interleaved flicker noise spectral artefacts and to increase the ADC immunity to input signal characteristics. Enhanced offset and time-skew calibration algorithms are developed to maximize the pe...

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Published in2018 IEEE Symposium on VLSI Circuits pp. 99 - 100
Main Authors Vaz, Bruno, Verbruggen, Bob, Erdmann, Christophe, Collins, Diarmuid, Mcgrath, John, Boumaalif, Ali, Cullen, Edward, Walsh, Darragh, Morgado, Alonso, Mesadri, Conrado, Long, Brian, Pathepuram, Rajitha, De La Torre, Ronnie, Manlapat, Alvin, Karyotis, Georgios, Tsaliagos, Dimitris, Lynch, Patrick, Peng Lim, Breathnach, Daire, Farley, Brendan
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
1f noise
ADC
Bandwidth
Calibration
chopping and flicker noise
Clocks
digital calibration
FinFETs
Photomicrography
time-interleaving
Very large scale integration
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DOI10.1109/VLSIC.2018.8502306

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Summary:A 13bit 5GS/s time-interleaved ADC is described which uses a chopping technique to reduce the effect of interleaved flicker noise spectral artefacts and to increase the ADC immunity to input signal characteristics. Enhanced offset and time-skew calibration algorithms are developed to maximize the performance in the presence of non-ideal sampling switches. At 5GS/s, the ADC dissipates 641mW while achieving a 62dB and 57dB of SFDR and SNDR respectively while maintaining a SFDR excluding HD2 and HD3 better than 70dBc across the first Nyquist band for input amplitudes down to -20dBFS.
DOI:10.1109/VLSIC.2018.8502306