Design of low-power variation tolerant signal processing systems with adaptive finite word-length configuration

• Published in: 2010 11th International Symposium on Quality Electronic Design (ISQED) pp. 372 - 379
• Main Authors: Yang Liu, Jibang Liu, Tong Zhang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2010
• Subjects: Adaptive filters; Adaptive signal processing; Adaptive systems; Circuit faults; Digital integrated circuits; Digital signal processing; Energy efficiency; Signal design; Signal processing algorithms; Timing
• ISBN: 9781424464548; 1424464544
• ISSN: 1948-3287; 1948-3295
• DOI: 10.1109/ISQED.2010.5450551

This paper concerns the design of low power digital signal processing integrated circuits in the presence of significant process variations. The basic idea is to leave smaller-than-worst-case timing margin for improving energy efficiency during the design phase and selectively reduce the finite word-length of circuit datapaths in post-silicon to eliminate all the timing faults during the run time. This simple idea can be intuitively justified by the fact that process variations may render only a few post-silicon datapaths to timing faults, while reducing the finite word-length of a few datapaths in signal processing systems may not necessarily make the overall algorithm-level performance unacceptable in run time. We present a design flow to implement this method and propose a dual finite word-length configuration strategy to simplify its real-life realization. Using linear low-pass filter and Turbo code decoder design at 45 nm node as case studies, we quantitatively demonstrate that this adaptive finite word-length configuration design strategy may effectively relax the timing margin and accordingly reduce the power consumption by over 18% over conventional worst-case design approach.