A Triple-Mode MAP/VA IP Design for Advanced Wireless Communication Systems

In this paper, a triple-mode MAP/VA IP for advanced wireless communication Systems is implemented in 0.18mum CMOS process. We employ triple-mode MAP/VA timing charts that can run two different algorithms at the same time by complementing the idle time of each other. In order to conform to the advanc...

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Bibliographic Details
Published in2005 IEEE Asian Solid-State Circuits Conference pp. 221 - 224
Main Authors Cheng-Hung Lin, Fan-Min Li, Xin-Yu Shi, An-Yeu Wu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2005
Subjects
Analytical models
Clocks
CMOS process
Communication standards
Frequency
Iterative decoding
Multiaccess communication
Throughput
Timing
Wireless communication
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Summary:In this paper, a triple-mode MAP/VA IP for advanced wireless communication Systems is implemented in 0.18mum CMOS process. We employ triple-mode MAP/VA timing charts that can run two different algorithms at the same time by complementing the idle time of each other. In order to conform to the advance communication standard, our IP can also perform as a reconfigurable trellis decoder. For WCDMA standard, this IP can operate at clock frequency of 100 MHz and achieve throughput rate of 4.17Mbps@6 iterations for turbo decoding and 1.56Mbps for convolutional decoding in concurrent MAP/VA mode from the worst-case static timing analysis and post-layout simulation
ISBN:0780391624
9780780391628
DOI:10.1109/ASSCC.2005.251705