Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS

This work proposes a DSP technique to mitigate the interference-induced spurious tones coupled to the digitally controlled oscillator (DCO) of a digital phase locked loop (DPLL). We leverage the digitized phase information at the time-to-digital converter (TDC) output, and formulate an adaptive algo...

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Bibliographic Details
Published inESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference pp. 213 - 216
Main Authors Cheng-Ru Ho, Chen, Mike Shuo-Wei
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2016
Subjects
Adaptive algorithms
Adaptive Filter
Adaptive filters
ADPLL
Couplings
Delays
DPLL
Interference
Interference Cancellation
Phase locked loops
Phase noise
PLL
Spur Cancellation
Spur Mitigation
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Summary:This work proposes a DSP technique to mitigate the interference-induced spurious tones coupled to the digitally controlled oscillator (DCO) of a digital phase locked loop (DPLL). We leverage the digitized phase information at the time-to-digital converter (TDC) output, and formulate an adaptive algorithm to identify the interference pattern from any electrical or magnetic coupling path, and inject the cancellation signal accordingly. The proposed algorithm also keeps track of the magnitude and phase variation in the background. We experiment with the algorithm in a 65nm 3-5 GHz DPLL prototype and observe 10 ~ 30 dB spur reduction from different coupling paths to the DCO over various interference frequencies. Additionally, the prototype measures reference spur of <;-110dBc and phase noise of - 129dBc/Hz at 3MHz offset frequency.
DOI:10.1109/ESSCIRC.2016.7598280