How to automate millions lines of top-level UVM testbench and handle huge register classes

Not only design automation, but also testbench (TB) automation heavily affects design period, so that diverse TB automation solutions have been developed and applied to the verifications ranging from IP level to top-level. Top-level verification environment is much more complex and big, approximatel...

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Bibliographic Details
Published in2012 International SoC Design Conference (ISOCC) pp. 405 - 407
Main Authors Namdo Kim, Young-Nam Yun, Young-Rae Cho, Kim, J. B., Byeong Min
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2012
Subjects
Automation
Data models
IP networks
Logic gates
Registers
SoC
System-on-a-chip
SystemVerilog
testbench
UVM
Verification
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Summary:Not only design automation, but also testbench (TB) automation heavily affects design period, so that diverse TB automation solutions have been developed and applied to the verifications ranging from IP level to top-level. Top-level verification environment is much more complex and big, approximately 2M lines of code (LOC), so automatic generation of top-level TB is an inevitable process for competitive design period. This paper presents an experience of SV (SystemVerilog) UVM (Universal Verification Methodology) TB automation on an over 100M gate top level SoC design. Most of the TB, 88% of 2M LOC except test scenarios and user codes, has been automatically generated by the proposed automation solution. The automation solution has strong flexibility and high level maintainability upon frequent specification changes. Also, the configurable TB for various DUTs resulted 50% simulation performance enhancement.
ISBN:1467329894
9781467329897
DOI:10.1109/ISOCC.2012.6407127