Implementation of kernels on the Maestro processor

Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maes...

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Bibliographic Details
Published in2013 IEEE Aerospace Conference pp. 1 - 6
Main Authors Jinwoo Suh, Kang, D. I. D., Crago, S. P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2013
Subjects
Clocks
Finite impulse response filters
Microprocessors
Multicore processing
Pipelines
Space vehicles
Vectors
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Summary:Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro processor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency. On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add, FIR filter, and FFT. We measured and analyzed the performance of these kernels. The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.
ISBN:9781467318129
1467318124
ISSN:1095-323X
2996-2358
DOI:10.1109/AERO.2013.6496949