Cost-performance analysis of component architectural designs for Dynamic Partially Reconfigurable Systems

• Published in: 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) pp. 1 - 6
• Main Authors: Diaz, D., Dumitriu, V., Kirischian, L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2012
• Subjects: Computer architecture; Equations; Field programmable gate arrays; Hardware; Mathematical model; parallel architectures; Program processors; reconfigurable architectures
• ISBN: 1467314315; 9781467314312
• ISSN: 0840-7789
• DOI: 10.1109/CCECE.2012.6334961

Dynamic Partially Reconfigurable Computing(DPRC) systems have received significant attention in recent years as a potential alternative to traditional computing system designs; such systems implement much of their functionality in the form of virtual components, represented by configuration bit-streams. However, for such systems to be adopted as viable mainstream solutions to system design, a number of problems and challenges must be addressed. One such challenge is the decision criteria for the selection of architectures for the components which make up such systems. This study explores the importance a cost-efficiency factor (CEF) has in the design of virtual components in embedded reconfigurable systems. Dedicated hardware, software, and hybrid architectures were analyzed for two video applications. The resulting analysis demonstrates that the selection of architectures for virtual components can benefit from considerations of the CEF and time-to-market associated with each architecture.