Design Space Exploration of an Execution-Driven Functional Simulation Methodology

• Published in: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) pp. 295 - 300
• Main Authors: Mahapatra, Ipsita Biswas, Agarwal, Utkarsh, Azad, Chandrashekhar, Nandy, S. K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2018
• Subjects: Computational modeling; Copper; Execution-driven simulation; Fabrics; Functional simulation; Hardware; Heuristic algorithms; Partitioning algorithms; Re-configurable hardware; Space exploration; VLSI
• ISSN: 2380-6923
• DOI: 10.1109/VLSID.2018.79

Exploration of an efficient functional simulation methodology that has the capability to encounter conflicting conditions such as: maximizing hardware occupancy using efficient partitioning and mapping algorithms and minimizing inter hardware communication using optimized hardware dimensions, is very important. In this paper, we explore the design space of an execution-driven functional simulation methodology named EX-DRIVE. It performs functional simulation of a design under test (DUT) without the need for hardware synthesis and implementation of the DUT, offering significant improvement in functional simulation time. To realize this methodology we use a Network of Interconnected HyperCells (NIHC) as the meta platform. We explore the design space of EX-DRIVE for various dimensions of NIHC fabric and different partitioning and mapping algorithms. For this study we investigate six different hardware dimensions having a fixed hardware capacity and three partitioning and mapping algorithms: a Discrete Particle Swarm Optimization based algorithm (DPSO), a heuristic and a convex algorithm. We find that, for a fixed hardware capacity, the heuristic and convex algorithm proves to be more efficient for large and densely connected DUTs whereas the DPSO based algorithm proves to be more efficient for smaller and sparsely connected data flow graphs. The proposed algorithms are generic enough to be applied to any coarse grained re-configurable array assisted functional simulation platform.