A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology

In this paper a RSA crypto coprocessor that is fabricated using a 0.18mum CMOS technology is presented. This processor combines a new version of high radix Montgomery multiplication algorithm with a super-pipeline design. With this algorithm, modular exponentiation can be decomposed into a series of...

Full description

Saved in:
Bibliographic Details
Published in2006 IFIP International Conference on Very Large Scale Integration pp. 216 - 221
Main Authors Xuemi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2006
Subjects
Acceleration
Algorithm design and analysis
Application specific integrated circuits
Cathode ray tubes
CMOS technology
Coprocessors
Field programmable gate arrays
Hardware
Pipelines
Public key cryptography
Online AccessGet full text

Cover

More Information
Summary:In this paper a RSA crypto coprocessor that is fabricated using a 0.18mum CMOS technology is presented. This processor combines a new version of high radix Montgomery multiplication algorithm with a super-pipeline design. With this algorithm, modular exponentiation can be decomposed into a series of primitive operation (PO) matrixes. All the POs are scheduled on the pipeline by employing column-sharing strategy, and inside the PO all the partial results are compressed first by Wallace tree to assure only one carry propagation in the critical path. With these optimizations, a decryption rate of 6.35 Mbps can be achieved for 1024-bit RSA
ISBN:3901882197
9783901882197
ISSN:2324-8432
DOI:10.1109/VLSISOC.2006.313236