Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells

N-channel and P-channel single-poly embedded flash (eflash) memory cells were implemented in a standard CMOS logic process. Among the different configurations based on standard I/O devices, the N-channel cell with a PMOS-PMOS-NMOS combo and the P-channel cell with an NMOS-NMOS-PMOS combo were found...

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Bibliographic Details
Published in2013 IEEE International Reliability Physics Symposium (IRPS) pp. MY.4.1 - MY.4.6
Main Authors Seung-Hwan Song, Jongyeon Kim, Kim, C. H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2013
Subjects
Couplings
Current measurement
Embedded Flash
Flash Program/Erase
Flash Reliability
Logic gates
Nonvolatile memory
Single-Poly Embedded Flash Cell
Temperature measurement
Transistors
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Summary:N-channel and P-channel single-poly embedded flash (eflash) memory cells were implemented in a standard CMOS logic process. Among the different configurations based on standard I/O devices, the N-channel cell with a PMOS-PMOS-NMOS combo and the P-channel cell with an NMOS-NMOS-PMOS combo were found to be most attractive in terms of program/erase performance, while the cell with a coupling device having P+ poly showed longer retention characteristic than the cells with a coupling device having N+ poly. Negligible program disturbance and floating gate coupling were observed in all cell types.
ISBN:9781479901128
1479901121
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2013.6532095