A distributed FIFO scheme for on chip communication

Interconnect delays are increasingly becoming the dominant source of performance degradation in the nanometer regime, largely because of disturbances that result from parasitic effects. On chip communication now requires multiple clock cycles for signal propagation between communicating modules/comp...

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Bibliographic Details
Published in2005 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1851 - 1854 Vol. 2
Main Authors Rydberg, R.R., Nyathi, J., Delgado-Frias, J.G.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
buffer
Clocks
Communication system control
Degradation
Delay effects
Frequency
Integrated circuit interconnections
interconnect
On-chip-communication
Repeaters
self-timed
System-on-a-chip
Temperature
Voltage
wave-pipelining
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Summary:Interconnect delays are increasingly becoming the dominant source of performance degradation in the nanometer regime, largely because of disturbances that result from parasitic effects. On chip communication now requires multiple clock cycles for signal propagation between communicating modules/components. Repeater insertion is widely used to improve global interconnect delays. We propose having distributed first-in-first-out buffers to facilitate communication between components/modules of highly integrated systems, such as system-on-chip. This stateful scheme has very good tolerance for voltage and temperature variations. The buffer control circuitry is self-timed and allows for ease of interfacing in multiple domain clock designs. We present the buffer and its associated control circuits that allow data transfers at a maximum frequency of 1.67 GHz in a 0.25 /spl mu/m technology.
ISBN:9780780388345
0780388348
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2005.1464971