32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE
We demonstrate that a 32Gb/s transmitter with a 4-way interleaved configuration is feasible in 28nm CMOS. A bit in the data stream contributes to a 2UI-wide pulse in the output signal, eliminating the need for 2-to-1 MUXs and enabling the use of quarter-rate clocking. A 4-tap 1UI-spacing FIR filter...
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Published in | 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers pp. 40 - 41 |
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Main Authors | , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.02.2013
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Subjects | |
Online Access | Get full text |
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Summary: | We demonstrate that a 32Gb/s transmitter with a 4-way interleaved configuration is feasible in 28nm CMOS. A bit in the data stream contributes to a 2UI-wide pulse in the output signal, eliminating the need for 2-to-1 MUXs and enabling the use of quarter-rate clocking. A 4-tap 1UI-spacing FIR filter is implemented in the transmitter to compensate for the signal loss in the signal transmission media. The output signal is compatible with conventional NRZ receivers with a DFE. |
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ISBN: | 9781467345156 1467345156 |
ISSN: | 0193-6530 2376-8606 |
DOI: | 10.1109/ISSCC.2013.6487628 |