A carbon nanotube transistor based RISC-V processor using pass transistor logic

• Published in: 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) pp. 1 - 6
• Main Authors: Amarnath, Aporva, Siying Feng, Pal, Subhankar, Ajayi, Tutu, Rovinski, Austin, Dreslinski, Ronald G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2017
• Subjects: Adders; CNTFETs; Delays; Logic gates; Silicon; Threshold voltage
• DOI: 10.1109/ISLPED.2017.8009156

With silicon-based transistors approaching their scaling limits, multiple successor technologies are competing for silicon's place. Due to recent fabrication breakthroughs, one promising alternative is the carbon nanotube field-effect transistor (CNTFET), which uses carbon nanotubes as the channel medium instead of silicon. Although logic gates using CNTFETs have been demonstrated to provide up to an order of magnitude better energy-delay product (EDP) over silicon-based counterparts, system-level design using CNTFETs show significantly smaller EDP improvement because of the critical path of the design, output load capacitance and corresponding drive strengths of gates. In this paper, we address this challenge by exploring various architectural design choices using CNTFET-based pass transistor logic (PTL) and create an energy-efficient RISC-V processor. While silicon-based design traditionally prefers complementary logic over PTL, CNTFETs are ideal candidates for PTL due to their low threshold voltage, low power dissipation, and equal strength p-type and n-type transistors. By utilizing PTL to design modules that lie on the processor's critical path, systems can efficiently exploit CNTFET's potential benefits. Our results show that while a CNTFET RISC-V processor using complementary logic achieves a 2.9× EDP improvement over a silicon design, using PTL along the critical path components in the ALU can boost EDP improvement 5× as well as reduce area by 17% over 16 nm silicon CMOS.