DFM reality in sub-nanometer IC design

The impact of sub-nanometer (below 90nm) effects on IC designs needs to be clearly understood to ensure that (1) manufacturing variations are considered during design to avoid catastrophic failures, and (2) the expected performance simulated in design is actually realized on silicon to avoid paramet...

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Bibliographic Details
Published in2007 Asia and South Pacific Design Automation Conference pp. 226 - 231
Main Authors Verghese, N., Hurat, P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2007
Subjects
Delay effects
Design engineering
Design for manufacture
Design methodology
Design optimization
Pulp manufacturing
Semiconductor device manufacture
Shape
Silicon
Virtual manufacturing
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Summary:The impact of sub-nanometer (below 90nm) effects on IC designs needs to be clearly understood to ensure that (1) manufacturing variations are considered during design to avoid catastrophic failures, and (2) the expected performance simulated in design is actually realized on silicon to avoid parametric failures. This paper discusses design for manufacturing solutions that enable designers to predict systematic manufacturing variations during design to detect and repair catastrophic and parametric failures. This paper presents real examples of design sensitivities to sub-nanometer manufacturing variations and the need to correctly analyze, optimize and verify the design before manufacturing by using appropriate EDA solutions which bring the effects of manufacturing variations in the design flow.
ISBN:1424406293
9781424406296
ISSN:2153-6961
2153-697X
DOI:10.1109/ASPDAC.2007.357990