Evaluation of phosphorus diffusion in the confined nano-wire under the influence of Si/SiO2 interface

• Published in: 2006 International Workshop on Nano CMOS pp. 136 - 145
• Main Authors: Seike, A., Sano, I., Yamada, K., Ohdomari, I.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2006
• Subjects: Dielectric films; diffusion; Dry etching; electrical properties; Electrodes; IV characterization; Lithography; MOSFETs; Nanoscale devices; phosphorus; pile-up; segregatkon; Si nanowire; Si/SiO 2 interface; SIMS; Thermal conductivity; Thermal stresses; Transistors; Wire
• ISBN: 142440603X; 9781424406036
• DOI: 10.1109/IWNC.2006.4570985

Diffusion of phosphorus is studied by means of electrical measurement of the Si-wire devices and SIMS profiles of bulk SOI. The conductivity of Si-wire decreases as the thermal budget increases. The sample of 80 nm in the designed width (W mask ), of which the actual width after the oxidation is 57.4 nm, has higher conductivity, which is the factor of 3 to 4.5, with respect to the theoretical value of bulk Si. We assume that the stress applied from the peripheral SiO 2 influence on the phosphorus diffusion in Si. Segregation of phosphorus ions at both cap-SiO 2 /Si(SOI) and Si(SOI)/SiO 2 (BOX) is recognized, however, no dependency of SIMS profiles on the thermal budget is confirmed. Dose loss of phosphorus due to the diffusion into the cap-SiO 2 is about 1*10 19 cm -3 . The result of dependency of conductivity on the thermal budged doesnpsilat coincide with the data of SIMS profiles. This is because the SIMS profile of bulk sample doesnpsilat provide the lateral information nor reflect the effect of stress from the peripheral SiO 2 film. Further investigation will be needed to reveal the relation between the size effect on the conductivity and the stress from the peripheral SiO 2 .