Position Paper: Extending Codelet Model for Dataflow Software Pipelining using Software-Hardware Co-Design

• Published in: 2019 IEEE 43rd Annual Computer Software and Applications Conference (COMPSAC) Vol. 2; pp. 640 - 645
• Main Authors: Raskar, Siddhisanket, Applencourt, Thomas, Kumaran, Kalyan, Gao, Guang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2019
• Subjects: Codelet Model; Computational modeling; Data models; Dataflow Model; Dataflow Software Pipelining; Exa-scale; FIFO Buffer; Hardware; Many-core Architecture; Optimization; Pipeline processing; Program Execution Model; Software; Software Pipelining
• ISBN: 9781728126074; 172812607X
• DOI: 10.1109/COMPSAC.2019.10280

Trends in processor and system architecture, driven by power and complexity, point super-computing landscape toward very high and heterogeneous core count designs. As the number of cores inevitably increase traditional ways of performing large scale computations will also need to evolve from legacy models like OpenMP & MPI. However, such models are very much wedded to a control-flow vision of parallel programs, making it difficult to express asynchrony in programs. To address these challenges, codelet model was developed which is fine-grained, event-driven asynchronous program execution model. In-spite of its initial design goals, the Codelet model is rife with opportunities for further improvements to provide high-performance for both data and control regular applications. The major inspiration behind this work is to leverage the decades of research done to exploit instruction level parallelism (ILP) for the machine instructions inside codelet while build upon the dataflow software pipelining principals at codelet graph level to further enhance performance. In this paper, we propose hardware assisted extensions to the original codelet program execution model in order to implement efficient dataflow software pipelining and extend capabilities of the codelet model. This hardware-software co-design focuses on efficient implementation of data FIFO buffers leveraging proposed optimizations like - FIFO ring buffers and multiple-head FIFO buffers and single owner FIFO buffers to further exploit advantages of dataflow software pipelining. The wide range of scientific, machine learning and specially streaming applications should be able to take advantage of techniques proposed in this paper. Identifying these kernels and bench-marking them are the next anticipated steps for us.