Characterisation and integration of Parylene as an insulating structural layer for high aspect ratio electroplated copper coils

This paper reports the development of processing methods and test structures for the characterisation and evaluation of Parylene-C as an insulating structural layer material for integration with planar micro-inductors. The process involves the filling of high aspect ratio gaps between copper structu...

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Bibliographic Details
Published in2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) pp. 7 - 12
Main Authors Walker, R., Sirotkin, E., Schmueser, I., Terry, J. G., Smith, S., Stevenson, J. T. M., Walton, A. J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2013
Subjects
Annealing
Coils
Copper
Semiconductor device measurement
Strain
Stress
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Summary:This paper reports the development of processing methods and test structures for the characterisation and evaluation of Parylene-C as an insulating structural layer material for integration with planar micro-inductors. The process involves the filling of high aspect ratio gaps between copper structures with Parylene and subsequent chemical mechanical planarisation. A test chip has been designed to characterise this process and the results presented. Subsequently complete micro-inductors, with magnetic cores, have been fabricated to demonstrate the capability of the process.
ISBN:9781467348454
1467348457
ISSN:1071-9032
2158-1029
DOI:10.1109/ICMTS.2013.6528137