Stochastic TDC architecture with self-calibration

• Published in: APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems pp. 1027 - 1030
• Main Authors: Ito, S, Nishimura, S, Kobayashi, H, Uemori, S, Tan, Y, Takai, N, Yamaguchi, T J, Niitsu, K
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2010
• Subjects: Built-in self-test; Calibration; Delay; Delay lines; Histograms; Linearity; Self-Calibration; Self-Testing; Simulation; Stochastic TDC; TDC

This paper describes a time-to-digital converter (TDC) architecture with fine time resolution, self-calibration and self-testing, and these features are realized by the following: (1) Encoder circuit that ensures monotonic characteristics. (2) Self-calibration circuit for linearity improvement. (3)...