Stochastic TDC architecture with self-calibration

This paper describes a time-to-digital converter (TDC) architecture with fine time resolution, self-calibration and self-testing, and these features are realized by the following: (1) Encoder circuit that ensures monotonic characteristics. (2) Self-calibration circuit for linearity improvement. (3)...

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Bibliographic Details
Published inAPCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems pp. 1027 - 1030
Main Authors Ito, S, Nishimura, S, Kobayashi, H, Uemori, S, Tan, Y, Takai, N, Yamaguchi, T J, Niitsu, K
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2010
Subjects
Built-in self-test
Calibration
Delay
Delay lines
Histograms
Linearity
Self-Calibration
Self-Testing
Simulation
Stochastic TDC
TDC
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Summary:This paper describes a time-to-digital converter (TDC) architecture with fine time resolution, self-calibration and self-testing, and these features are realized by the following: (1) Encoder circuit that ensures monotonic characteristics. (2) Self-calibration circuit for linearity improvement. (3) Stochastic architecture for fine time resolution. (4) Self-testing for reliability requirements. These features can be implemented with an advanced fine CMOS process using digital design methodology. The circuit structure and operation are described, and MATLAB simulation results are presented.
ISBN:142447454X
9781424474547
DOI:10.1109/APCCAS.2010.5774740