A test structure for characterization of CMOS APS

A test structure to characterize CMOS APS image sensor is presented. Individual photodiodes and pixels as well as an image sensor array of 64/spl times/64 active pixels with selectable linear or logarithmic operation modes are designed. A test chip includes these features in addition to on-chip timi...

Full description

Saved in:
Bibliographic Details
Published inProceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) pp. 151 - 154
Main Authors Elkhatib, T.A., Moussa, S., Ragaie, H.F., Haddara, H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Circuit testing
CMOS image sensors
Digital circuits
Digital control
Image sampling
Image sensors
Photodiodes
Pixel
Sensor arrays
Timing
Online AccessGet full text

Cover

More Information
Summary:A test structure to characterize CMOS APS image sensor is presented. Individual photodiodes and pixels as well as an image sensor array of 64/spl times/64 active pixels with selectable linear or logarithmic operation modes are designed. A test chip includes these features in addition to on-chip timing and control digital circuits as well as correlated double sampling have been built on a 0.6 /spl mu/m CMOS process. The test methodology and preliminary simulation results are presented.
ISBN:9770520101
9789770520109
DOI:10.1109/ICM.2003.238501