Study of Dynamic Warpage of Flip Chip Packages under Temperature Reflow

Flip chip deforms after assembly due to coefficient of thermal expansion mismatch of silicon and substrate coupled with underfills. Issues arise when excessive package warpage leads to improper joint during surface mount technology and increase in assembly yield loss. In this paper, application of s...

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Bibliographic Details
Published in2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium pp. 185 - 190
Main Authors Chee Kan Lee, Wei Keat Loh, Kang Eu Ong, Chin, I.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2006
Subjects
Assembly
Finite element methods
Flip chip
Packaging
Silicon
Solid modeling
Surface-mount technology
Temperature
Thermal expansion
Thermomechanical processes
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Summary:Flip chip deforms after assembly due to coefficient of thermal expansion mismatch of silicon and substrate coupled with underfills. Issues arise when excessive package warpage leads to improper joint during surface mount technology and increase in assembly yield loss. In this paper, application of shadow moire technique and finite element modeling approach were introduced to study the thermo-mechanical response of various package types, material set and geometrical parameters example silicon die and substrate size. Finite element modeling results showed the package geometry has more influence on warpage with die and package size parameter for package without integrated heat spreader (I-HS).
ISBN:9781424407293
142440729X
ISSN:1089-8190
2576-9626
DOI:10.1109/IEMT.2006.4456453