Design and Simulation of an Improved Soft-Switched Synchronous Buck Converter

This paper proposes an improved soft switched synchronous buck converter in a fixed load condition. The switching energy can be fully recovered during current commutation phase in the gate driver while the diode conduction losses in the low and high side switches can be substantially reduced by empl...

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Bibliographic Details
Published in2009 Third Asia International Conference on Modelling & Simulation pp. 751 - 756
Main Authors Yahaya, N.Z., Begam, K.M., Awan, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2009
Subjects
Buck converters
Circuit simulation
Diodes
Driver circuits
PSpice Simulation
Pulse generation
Resonance
Resonant Gate Driver
RLC circuits
Signal generators
Soft Switching
Switches
Switching circuits
Synchronous Buck Converter
ZVS
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Summary:This paper proposes an improved soft switched synchronous buck converter in a fixed load condition. The switching energy can be fully recovered during current commutation phase in the gate driver while the diode conduction losses in the low and high side switches can be substantially reduced by employing additional L and C resonant in the circuit. Using PSpice simulation, the optimization technique has been studied. From the predetermined pulse width of the generated signals, the optimized resonant inductor current is observed to generate less oscillation and hence lower the switching loss. In addition, an optimized dead time interval is inserted between high side and low side of the transistors in the synchronous buck converter to minimize their body diode conduction losses. The detailed operations of both circuits are analyzed.
ISBN:9781424441549
1424441544
ISSN:2376-1164
DOI:10.1109/AMS.2009.62