First integration of Cu TSV using die-to-wafer direct bonding and planarization

Copper-filled Through-Si Vias (TSV) with diameters from 2 mum to 5 mum have been integrated in a die-to-wafer stack combining direct bonding and a planarization technique. TSVs were processed on chip backside after oxide bonding and substrate thinning. The results were compared to the ones achieved...

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Bibliographic Details
Published in2009 IEEE International Conference on 3D System Integration pp. 1 - 5
Main Authors Leduc, P., Assous, M., Di Cioccio, L., Zussy, M., Signamarcheix, T., Roman, A., Rousseau, M., Verrun, S., Bally, L., Bouchu, D., Cadix, L., Farcy, A., Sillon, N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2009
Subjects
3D integration
Copper
die to wafer stacking
Etching
Planarization
Scanning electron microscopy
Silicon
Stacking
Substrates
Testing
Through-silicon vias
TSV
Wafer bonding
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Summary:Copper-filled Through-Si Vias (TSV) with diameters from 2 mum to 5 mum have been integrated in a die-to-wafer stack combining direct bonding and a planarization technique. TSVs were processed on chip backside after oxide bonding and substrate thinning. The results were compared to the ones achieved with a wafer-to-wafer test vehicle. It was demonstrated that die-to-wafer process developed for this integration does not impact TSV electrical and morphological properties. Moreover, no damage was observed on the stack during TSV process performed at 400 degC. This demonstration is the first step to validate the industrial compatibility between high density TSV process and die-to-wafer direct bonding and planarization techniques. With a resistance close to 150 mohm and a capacitance of about 30 fF, 3 mum-diameter TSV provides excellent electrical performance to heterogeneous 3D ICs.
ISBN:9781424445110
1424445116
DOI:10.1109/3DIC.2009.5306602