Leakage optimization of thick oxide IO/ESD transistors in 40nm global foundry process

Thick Oxide IO/ESD transistor in 40nm Global Foundry process is studied for reducing leakage while being area efficient and maintaining performance. Gate induced drain leakage(GIDL) and source-drain leakage were found to be the major leakage contributors. Optimum architecture and sizing are found fo...

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Bibliographic Details
Published in2017 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia) pp. 84 - 87
Main Authors Panigrahi, Chinmayee, Rastogi, Mansi, Gopal, Kiran
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2017
Subjects
40nm GFCMOS
Computer architecture
GIDL
IO/ESD
Logic gates
Low power design
Microprocessors
MOS devices
Subthreshold current
Transistors
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Summary:Thick Oxide IO/ESD transistor in 40nm Global Foundry process is studied for reducing leakage while being area efficient and maintaining performance. Gate induced drain leakage(GIDL) and source-drain leakage were found to be the major leakage contributors. Optimum architecture and sizing are found for IO/ESD design and presented in this paper.
DOI:10.1109/ICCE-ASIA.2017.8309321