Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter

• Published in: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) pp. 283 - 288
• Main Authors: Khan, Mohd. Tasleem, Ahamed, Shaik Rafi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2018
• Subjects: Clocks; Complexity theory; Distributed Arithmetic (DA); finite impulse response (FIR); Finite impulse response filters; Hardware; look up table (LUT); offset binary coding (OBC); Registers; Table lookup; Very large scale integration
• ISSN: 2380-6923
• DOI: 10.1109/VLSID.2018.77

This paper presents a new area and power efficient VLSI architecture for least-mean-square (LMS) adaptive filterusing distributed arithmetic (DA). Conventionally, DA basedLMS adaptive filter requires look-up tables (LUTs) for filteringand weight updating operations. The size of LUTs grows exponentially with filter order. The proposed scheme has reducedthe LUT size to half by storing the offset-binary-coding (OBC) combinations of filter weights and input samples. To make theadaptive filter more area and power efficient, it is not necessary todecompose LUT into two smaller LUTs. Hence, by using the nondecomposed LUT the proposed design achieves significant savingsin area and power over the best existing scheme. In addition, the proposed architecture involves comparatively lesser hardwarecomplexity for the same LUT-size. From synthesis results, it isfound that the proposed design with 32nd order filter offers 19.83% less area and consumes 20.54 % less power; utilizes 16.67 %and 19.04 % less number of LUT and FF respectively over thebest existing scheme.