An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS

An energy efficient reconfigurable processor for deep neural networks with binary/ternary weights and 1/2/4/8/16-bit activations is implemented in 28nm technology. Three technologies, Total- Partial- Pixel-Summation (TPPS), Kernel-Transformation-Data-Reconstruction (KTDR) and Hybrid Load-Balancing M...

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Bibliographic Details
Published in2018 IEEE Symposium on VLSI Circuits pp. 37 - 38
Main Authors Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
Adders
Convolution
Energy efficiency
Kernel
Microsoft Windows
Random access memory
Very large scale integration
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DOI10.1109/VLSIC.2018.8502388

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Summary:An energy efficient reconfigurable processor for deep neural networks with binary/ternary weights and 1/2/4/8/16-bit activations is implemented in 28nm technology. Three technologies, Total- Partial- Pixel-Summation (TPPS), Kernel-Transformation-Data-Reconstruction (KTDR) and Hybrid Load-Balancing Mechanism (HLBM), are employed to improve energy efficiency. Measurement results show that the energy efficiency of at most 95.8 TOPS/w for BWN, and 95.1 TOPS/W for TWN and 765.6 TOPS/w for BNN is achieved, and it shows 6.6x higher over state-of-the-art works.
DOI:10.1109/VLSIC.2018.8502388