A Double Capacitive Body Biased Circuit for High Performance Domino Logic with CMOS Keeper

In this paper, a double capacitive body biased keeper (DCBBK) for domino logic gate is proposed. By using this technique, the threshold voltage of keeper transistor is adapted to multi operating phase to reduce leakage power consumption and enhance speed compare to other techniques such as standard...

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Bibliographic Details
Published in2006 First International Conference on Communications and Electronics pp. 379 - 381
Main Authors Tung, H.T., Thang, N.V., Khanh, P.X., Kim, S.W.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2006
Subjects
Clocks
CMOS logic circuits
CMOS technology
Delay
Design engineering
double capacitive body bias keeper (DCBBK)
dynamic body bias keeper(DBBK)
Energy consumption
Immune system
Industrial electronics
Logic design
single capacitive body bias keeper(SCBBK)
Standard domino(SD) logic
Threshold voltage
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Summary:In this paper, a double capacitive body biased keeper (DCBBK) for domino logic gate is proposed. By using this technique, the threshold voltage of keeper transistor is adapted to multi operating phase to reduce leakage power consumption and enhance speed compare to other techniques such as standard domino (SD) without body bias, dynamic body biased keeper (DBBK) and single capacitive body biased keeper (SCBBK). All the various body biased circuits are applied to a wide fan in OR domino gate for evaluating delay time, power consumption, power-delay product (PDF) and noise immunity. The simulation results with 0.18 mum Hynix CMOS technology show that DCBBK reduces 44%, 22%, 9% in power compare to SD, DBBK, SCBBK while DBBK, SCBBK, DCBBK all improve 46% in speed than SD gate.
ISBN:9781424405688
1424405688
DOI:10.1109/CCE.2006.350790