Adaptive Simulated Annealer for high level synthesis design space exploration

• Published in: 2009 International Symposium on VLSI Design, Automation and Test pp. 106 - 109
• Main Authors: Schafer, B.C., Takenaka, T., Wakabayashi, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2009
• Subjects: Algorithm design and analysis; Cost function; Delay; Hardware; High level languages; High level synthesis; Simulated annealing; Space exploration; System performance; Timing
• ISBN: 1424427819; 9781424427819
• DOI: 10.1109/VDAT.2009.5158106

This paper presents a microarchitectural design space exploration tool called cwbexplorer based on an Adaptive Simulated Annealer Exploration Algorithm (ASA-ExpA) for behavioral descriptions written in untimed C or SystemC. Cwbexplorer automatically generates a series of designs given a set of constraints (area and latency) from an untimed high level language description. A commercial high level synthesis tool (Cy- berWorkBench) is used to synthesize each new architecture. The ASA-ExpA searches the design space based on the results of the previous synthesis, the global cost function and the given constraints. The global cost function weights are adaptively modified during the exploration to adjust the objective to minimize area or latency. Experimental results show that cwbexplorer successfully searches the design space fast and efficiently finding the smallest and fastest designs for most benchmarks, incurring in small penalties (5% in area and 8% in latency) for larger benchmarks while reducing the total runtime by an average of 66% compared to a brute force approach.