STI techniques for isolation of RF-SOI devices

Shallow trench isolation (STI) plays an important role in preventing current leakage between active semiconductor regions and enables the industry to scale device density. STI is created early during the device fabrication process, before transistors are formed. There are mainly two ways to create t...

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Bibliographic Details
Published in2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) pp. 1 - 2
Main Authors Adusumilli, Siva P, Shank, Steven M, Ellis-Monaghan, John, Teng, Chu-hsiang, Levy, Mark D, Stamper, Anthony K
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2017
Subjects
Dielectrics
Performance evaluation
Radio frequency
Silicon
Silicon-on-insulator
Stress
Substrates
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Summary:Shallow trench isolation (STI) plays an important role in preventing current leakage between active semiconductor regions and enables the industry to scale device density. STI is created early during the device fabrication process, before transistors are formed. There are mainly two ways to create the isolation: through oxide growth between active shapes (referred to as LOCOS), and by etching the trenches, filling with dielectric and removing the excessive dielectric using chemical-mechanical planarization, which is a CMP based STI technique. CMP STI can be done in 3 ways namely direct, mask aligned (Process A) and self-aligned (Process B).
DOI:10.1109/S3S.2017.8309255