A novel CMOS detector based on a deep trapping gate

• Published in: IEEE Nuclear Science Symposuim & Medical Imaging Conference pp. 655 - 658
• Main Author: Fourches, N T
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2010
• Subjects: Charge carrier processes; CMOS integrated circuits; Impurities; Logic gates; Pixel; Sensors; Silicon
• ISBN: 9781424491063; 1424491061
• ISSN: 1082-3654; 2577-0829
• DOI: 10.1109/NSSMIC.2010.5873840

A novel detecting device compatible with modified CMOS processes was studied using standard simulation codes. The physical principle of the device derives from the properties of a buried gate containing deep trapping centers. This gate, which modulates the drain-source current of the n or p MOS transistor selectively traps carriers generated by an impinging particle. This principle evaluated with realistic simulations parameters shows that a good signal to noise ratio might be obtained for an energy deposition equivalent to a minimum ionizing particle within a limited silicon thickness. Problems related to the physical implementation process for such a device are also discussed.