A 4-Bits Trimmed CMOS Bandgap Reference with an Improved Matching Modeling Design
Component tolerances and mismatches due to process variations severely degrade the performance of bandgap reference (BGR) circuits. In this paper, the authors describe the design of a BGR considering the Pelgrom's mismatch model. The main purpose of our methodology is to convey the design to re...
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Published in | 2007 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1911 - 1914 |
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Main Authors | , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.05.2007
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Subjects | |
Online Access | Get full text |
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Summary: | Component tolerances and mismatches due to process variations severely degrade the performance of bandgap reference (BGR) circuits. In this paper, the authors describe the design of a BGR considering the Pelgrom's mismatch model. The main purpose of our methodology is to convey the design to reach a good trade-off between area and mismatch. Implemented in standard 0.35μm CMOS technology, the circuit also includes a straightforward 4-bits trimming circuit to achieve more process variations independence. Its Monte Carlo temperature coefficient average is 40-ppm/°C and the reference output voltage average is 1.230V. The area of the BGR is 400x350μm 2 due to our design matching requirements. |
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ISBN: | 1424409209 9781424409204 |
ISSN: | 0271-4302 2158-1525 |
DOI: | 10.1109/ISCAS.2007.378348 |