Controllable Arbitrary Integer Frequency Divider Based on VHDL

• Published in: 2009 International Joint Conference on Artificial Intelligence pp. 691 - 694
• Main Authors: Tian Hongli, Shi Shuo, Zhang Jun, Zhao Hongdong
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2009
• Subjects: 50% duty cycle; Circuit synthesis; CPLD; Design methodology; Field programmable gate arrays; FPGA; Frequency conversion; frequency divider; Frequency synthesizers; Hardware design languages; Process design; Programmable logic arrays; Programmable logic devices; Very high speed integrated circuits; VHDL
• ISBN: 9780769536156; 0769536158
• DOI: 10.1109/JCAI.2009.62

The key technique for the design of a frequency divider is to find a function between the input and output. In general, the design process and circuit of a frequency divider is complicated, modification and transplantation for it is difficult. A creative design method of CAIFD (Controllable Arbitrary Integer Frequency Divider) is presented in this paper, which uses the VHDL (VHSIC Hardware Description Language ) source code to synthesize a FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device) circuit that produces a 50% duty cycle n (n is a integer and n>0 ) controllable waveform. In order to validate the design method, CAIFD which has different frequency coefficients is simulated in device of ALTERA Corporation's EP2S15F484C3. Results of the experiment shows that modification and transplantation of CAIFD is easy, moreover the performance is steady and reliable.