Variation-tolerant Design Using Residue Number System

In this paper the use of residue arithmetic is proposed as a technique to reduce delay variation in adders. It is found that the use of residue arithmetic offers significant delay variation reduction when compared to adders of the literature. Therefore this technique can be used to control variance...

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Bibliographic Details
Published in2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools pp. 157 - 163
Main Authors Kouretas, I., Paliouras, V.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2009
Subjects
Added delay
Adders
Arithmetic
Computer architecture
Data processing
Design engineering
Design methodology
Digital systems
Gaussian distribution
residue
RNS
SSTA
statistical
Timing
variation
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Summary:In this paper the use of residue arithmetic is proposed as a technique to reduce delay variation in adders. It is found that the use of residue arithmetic offers significant delay variation reduction when compared to adders of the literature. Therefore this technique can be used to control variance of critical paths delay and efficiently meet timing constraints and thus improve timing yield. Experiments conducted span several values of intra-die and die-to-die variance, so that cases of practical interest for various nanoscale technologies are covered.
ISBN:9780769537825
0769537820
DOI:10.1109/DSD.2009.160