A micro-network on chip with 10-Gb/s transmission link

In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is...

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Bibliographic Details
Published in2009 IEEE Asian Solid-State Circuits Conference pp. 277 - 280
Main Authors Wei-Chang Liu, Chih-Hsien Lin, Shyh-Jye Jou, Hung-Wen Lu, Chau-Chin Su, Kai-Wei Hong, Kuo-Hsing Cheng, Shyue-Wen Yang, Ming-Hwa Sheu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2009
Subjects
Circuits
Clocks
CMOS technology
Energy consumption
Microswitches
Prototypes
System-on-a-chip
Transceivers
Voltage
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Summary:In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13 ¿m CMOS technology. The core area of this chip is 990 ¿m*1600 ¿m and the power consumption is 155 mW (60 mW for micro-switches and 95 mW for 10-Gb/s data transceiver) at 1.2 V supply voltage with 10-Gb/s transmission data rate.
ISBN:1424444330
9781424444335
DOI:10.1109/ASSCC.2009.5357256