Interconnect failure due to voltage and humidity in a 30V BCD technology

This paper describes a failure mechanism that caused open-circuit failures in the interconnect layers of several ICs fabricated in a 30 V Bipolar-CMOS-DMOS (BCD) technology under highly-accelerated stress testing (HAST). A detailed failure analysis is presented, showing that there were several contr...

Full description

Saved in:
Bibliographic Details
Published in2009 21st International Symposium on Power Semiconductor Devices & IC's pp. 212 - 215
Main Authors Disney, D., Blattner, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2009
Subjects
Failure analysis
Humidity
Integrated circuit testing
Metallization
Passivation
Product design
Qualifications
Stress
Temperature
Voltage
Online AccessGet full text

Cover

More Information
Summary:This paper describes a failure mechanism that caused open-circuit failures in the interconnect layers of several ICs fabricated in a 30 V Bipolar-CMOS-DMOS (BCD) technology under highly-accelerated stress testing (HAST). A detailed failure analysis is presented, showing that there were several contributing factors to this failure mechanism, including top metal thickness, passivation stress, package-induced stress, interconnect voltage, and humidity.
ISBN:9781424435258
1424435250
ISSN:1063-6854
1946-0201
DOI:10.1109/ISPSD.2009.5158039