The design methodology and implementation of a first-generation CELL processor: a multi-core SoC

• Published in: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 pp. 45 - 49
• Main Authors: Pham, D., Behnen, E., Bolliger, M., Hofstee, H.P., Johns, C., Kahle, J., Kameyama, A., Keaty, J., Le, B., Masubuchi, Y., Posluszny, S., Riley, M., Suzuoki, M., Wang, M., Warnock, J., Weitzel, S., Wendel, D., Yazawa, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Clocks; Content management; Design methodology; Frequency; Hardware; Linux; Operating systems; Power system protection; Real time systems; Thermal management
• ISBN: 9780780390232; 0780390237
• ISSN: 0886-5930; 2152-3630
• DOI: 10.1109/CICC.2005.1568604

This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuing system integration trends. This paper then describes the implementation of a first-generation CELL processor and the design methods used to overcome the above challenges. A CELL processor consists of a 64 bit power architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multicore SoC, implemented in 90nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.