A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical r...

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Bibliographic Details
Published in2016 IEEE International Test Conference (ITC) pp. 1 - 7
Main Authors Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2016
Subjects
Algorithm design and analysis
built-in self-repair
built-in self-test
Circuit faults
Decoding
DRAM
Maintenance engineering
Random access memory
Redundancy
redundancy analysis
Registers
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Summary:With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.
ISSN:2378-2250
DOI:10.1109/TEST.2016.7805832