Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory

• Published in: 2014 IEEE 32nd International Conference on Computer Design (ICCD) pp. 16 - 21
• Main Authors: Mengying Zhao, Liang Shi, Chengmo Yang, Xue, Chun Jason
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2014
• Subjects: Benchmark testing; Educational institutions; Phase change materials; Radiation detectors; Random access memory; Registers; Round robin
• ISSN: 1063-6404; 2576-6996
• DOI: 10.1109/ICCD.2014.6974656

Phase change memory (PCM) has demonstrated great potential as an alternative of DRAM to serve as main memory due to its favorable characteristics of non-volatility, scalability and near-zero leakage power. However, the comparatively poor endurance of PCM largely limits its adoption. Wear leveling strategies targeting to even write distributions have been proposed at different granularities and on various memory hierarchies for PCM endurance enhancement. Write operations are distributed across the memory through migrating data from heavily written locations to less burdened ones, which is usually guided by counters recording the number of writes. However, evenly distributing writes at a coarse granularity cannot deliver the best endurance results as write distributions are highly imbalanced even at the bit level. In this work, we propose a near-zero-cost bit-level wear leveling strategy to improve PCM endurance. The proposed technique can be combined with various coarse-grained wear leveling strategies. Experiment results show 102% endurance enhancement on average, which is 34% higher than the most related work, with significantly lower storage, performance and energy overheads.