Development of graphene FETs for high frequency electronics

Recent advances in fabricating, measuring, and modeling of top-gated graphene FETs for high-frequency electronics are reviewed. By improving the oxide deposition process and reducing series resistance, an intrinsic cut-off frequency as high as 50 GHz is achieved in a 350-nm-gate graphene FET at a dr...

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Bibliographic Details
Published in2009 IEEE International Electron Devices Meeting (IEDM) pp. 1 - 4
Main Authors Yu-Ming Lin, Jenkins, K., Farmer, D., Valdes-Garcia, A., Avouris, P., Chun-Yung Sung, Hsin-Ying Chiu, Ek, B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2009
Subjects
Circuit synthesis
Current measurement
Cutoff frequency
Density measurement
Electrical resistance measurement
FETs
Frequency measurement
Gain measurement
MOSFETs
Silicon carbide
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Summary:Recent advances in fabricating, measuring, and modeling of top-gated graphene FETs for high-frequency electronics are reviewed. By improving the oxide deposition process and reducing series resistance, an intrinsic cut-off frequency as high as 50 GHz is achieved in a 350-nm-gate graphene FET at a drain bias of 0.8 V. This f T value is the highest frequency reported to date for any graphene transistor, and it also exceeds that of Si MOSFETs at the same gate length, illustrating the potential of graphene for RF applications.
ISBN:9781424456390
1424456398
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2009.5424378