A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems

• Published in: 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) pp. 5289 - 5292
• Main Authors: Aadithya, K. V., Yingyan Lin, Chenjie Gu, Aolin Xu, Roychowdhury, J., Shanbhag, N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2012
• Subjects: Analytical models; Clocks; Communication systems; Latches; Predictive models; Solid modeling; SPICE
• ISBN: 1467300454; 9781467300452
• ISSN: 1520-6149; 2379-190X
• DOI: 10.1109/ICASSP.2012.6289114

The design of a communications system is typically most effective only when each of its components can be accurately represented by a discrete, symbolic behavioural abstraction. Such abstractions, in addition to providing valuable design intuition, also enable highly efficient and scalable system-level simulation. However, given a SPICE-level description for a subsystem such as a latch, it is a challenge to come up with a discrete, symbol-level abstraction that accurately captures its continuous-time dynamics. Indeed, the manual construction of such an abstraction requires deep knowledge and understanding of the operation of the module in question; moreover, it is very time-consuming, tedious, error-prone and not easily scalable to larger designs. In recent work [1], we adapted methods from computational learning theory to develop an automated technique, DAE2FSM, that produces binary finite state machine (FSM) abstractions of non-linear analog/mixed-signal (AMS) circuits. In the present paper, we demonstrate the application of the DAE2FSM technique to automatically derive FSM abstractions for a mixed-signal communications circuit component, namely a current mode latch (CML) designed in IBM's 90nm LP process technology. We show that the FSMs learned by DAE2FSM not only capture the essence of the latch's behaviour during normal conditions, but also faithfully mimic its behaviour under adverse operating conditions (e.g., under lowered supply voltages). Moreover, in addition to a stand-alone CML, we also generate FSMs for cascades of two and three latches (such topologies are used in the design of power-efficient, bit-error optimised analog-to-digital converters). In spite of the inherent non-linearity of such systems, and in spite of the pronounced "analog-ness" of the waveforms in question, our FSM abstractions are able to produce discrete-time symbol sequences that closely match the data points obtained by sampling from continuous-time SPICE simulations.