A new synchronization policy between PSL checkers and SystemC designs at transaction level

• Published in: International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006 pp. 85 - 90
• Main Authors: Lahbib, Y., Ghrab, M.-A., Hechkel, M., Ghenassia, F., Tourki, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2006
• Subjects: Clocks; Computer bugs; Consumer electronics; Hardware; Laboratories; Microelectronics; Object oriented modeling; Runtime; Specification languages; Synchronization
• ISBN: 0780397266; 9780780397262
• DOI: 10.1109/DTIS.2006.1708698

The authors present a technique to synchronize between PSL (property specification language) checkers and SystemC IPs at the highest abstraction level of the ST Microelectronics system flow: transaction level modeling (TLM). A new assertion-based verification approach is proposed. It consists of a runtime simulation of the system-on-chip (SoC) under verification with PSL checkers. In this approach, the PSL checkers that represent the system specification are converted into C++ and therefore into a SystemC-TLM modules, which refer to us as TLM checkers. However, when integrating TLM checkers with SystemC models of SoC, the traditional clock-based synchronization at register transfer level and lower could not be applied. In fact, at the TLM abstraction level, the modeling rules forbid the use of a hardware clock. A new synchronization policy should be then proposed, hence the aim of this paper