A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput

• Published in: Digest of technical papers - IEEE International Solid-State Circuits Conference pp. 340 - 342
• Main Authors: Lee, Seungjae, Kim, Chulbum, Kim, Minsu, Joe, Sung-min, Jang, Joonsuc, Kim, Seungbum, Lee, Kangbin, Kim, Jisu, Park, Jiyoon, Lee, Han-Jun, Kim, Minseok, Lee, Seonyong, Lee, SeonGeon, Bang, Jinbae, Shin, Dongjin, Jang, Hwajun, Lee, Deokwoo, Kim, Nahyun, Jo, Jonghoo, Park, Jonghoon, Park, Sohyun, Rho, Youngsik, Park, Yongha, Kim, Ho-joon, Lee, Cheon An, Yu, Chungho, Min, Youngsun, Kim, Moosung, Kim, Kyungmin, Moon, Seunghyun, Kim, Hyunjin, Choi, Youngdon, Ryu, YoungHwan, Choi, Jinwon, Lee, Minyeong, Kim, Jungkwan, Choo, Gyo Soo, Lim, Jeong-Don, Byeon, Dae-Seok, Song, Kiwhan, Park, Ki-Tae, Kyung, Kye-hyun
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2018
• Subjects: Bit error rate; Computer architecture; Degradation; Flash memories; Programming; Sensors; Three-dimensional displays
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2018.8310323

Since the first demonstration of a production quality three-dimensional (3D) stacked-word-line NAND Flash memory [1], the 3b/cell 3D NAND Flash memory has seen areal density increases of more than 50% per year due to the aggressive development of 3D-wordline-stacking technology. This trend has been consistent for the last three consecutive years [2-4], however the storage market still requires higher density for diverse digital applications. A 4b/cell technology is one promising solution to increase bit density [5]. In this paper, we propose a 4b/cell 3D NAND Flash memory with a 12MB/s program throughput. The chip achieves a 5.63Gb/mm 2 areal density, which is a 41.5% improvement as compared to a 3b/cell NAND Flash memory in the same 3D-NAND technology [4].