A frequency-domain high-speed bus signal integrity compliance model: Design methodology and implementation

This paper investigates channel/link frequency domain compliance in order to predict compatibility with a bus's chip I/O circuitry at its ends. Any channel can be associated with certain frequency domain parameter values which are easily calculated from the channel S-parameter matrix. A set of...

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Bibliographic Details
Published in2015 IEEE 65th Electronic Components and Technology Conference (ECTC) pp. 545 - 550
Main Authors Win, Si T., Hejase, Jose A., Becker, Wiren D., Wiedemeier, Glen A., Dreps, Daniel M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2015
Subjects
Crosstalk
Frequency-domain analysis
Genetic algorithms
Insertion loss
Time-domain analysis
Wiring
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Summary:This paper investigates channel/link frequency domain compliance in order to predict compatibility with a bus's chip I/O circuitry at its ends. Any channel can be associated with certain frequency domain parameter values which are easily calculated from the channel S-parameter matrix. A set of frequency domain parameters that can sufficiently describe a channel are defined in this paper. Using a genetic algorithm, the frequency domain parameter bounds in a multidimensional space describing PCIe-Gen3 (bus speed = 8 Gb/s) compliant channels are found. Details of the methodology used in order to arrive at the multidimensional frequency domain compliance model, model results and model simulation validation testing are presented.
ISSN:0569-5503
2377-5726
DOI:10.1109/ECTC.2015.7159643