Property analysis and design understanding

• Published in: 2009 Design, Automation & Test in Europe Conference & Exhibition pp. 1246 - 1249
• Main Authors: Kuhne, U., Grosse, D., Drechsler, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2009
• Subjects: Circuit simulation; Circuit testing; Circuits and systems; Computer science; Design automation; Design engineering; Design methodology; Formal verification; Hardware; Writing
• ISBN: 9781424437818; 1424437814
• ISSN: 1530-1591; 1558-1101
• DOI: 10.1109/DATE.2009.5090855

Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are several techniques that can check if a set of formal properties forms a complete specification of a design. But, in contrast to simulation-based methods, like random testing, formal verification requires a detailed knowledge of the design implementation. Finding the correct set of properties is a tedious and time consuming process. In this paper, two techniques are presented that provide automatic support for writing properties in a quality-driven BMC flow. The first technique can be used to analyze properties in order to remove redundant assumptions and to separate different scenarios. The second technique - inverse property checking - automatically generates valid properties for a given expected behavior. The techniques are integrated with a coverage check for BMC. Using the presented techniques, the number of iterations to obtain full coverage can be reduced, saving time and effort.