Challenges and limitations of NAND flash memory devices based on floating gates

In this paper, the limitations and challenges of NAND flash memory devices based on floating gates are discussed. And, the newly adopted operation algorithms, such as intelligent incremental step pulse erase, various biasing in grouped W/Ls, virtual negative read and data randomization, and their re...

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Bibliographic Details
Published in2012 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 420 - 423
Main Authors Byoungjun Park, Sunghoon Cho, Milim Park, Sukkwang Park, Yunbong Lee, Myoung Kwan Cho, Kun-Ok Ahn, Gihyun Bae, Sungwook Park
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2012
Subjects
Computer architecture
Flash memory
Interference
Logic gates
Microprocessors
Nonvolatile memory
Reliability
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Summary:In this paper, the limitations and challenges of NAND flash memory devices based on floating gates are discussed. And, the newly adopted operation algorithms, such as intelligent incremental step pulse erase, various biasing in grouped W/Ls, virtual negative read and data randomization, and their results are exhibited.
ISBN:9781467302180
146730218X
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2012.6272053