Compute Caches

This paper presents the Compute Cache architecture that enables in-place computation in caches. Compute Caches uses emerging bit-line SRAM circuit technology to re-purpose existing cache elements and transforms them into active very large vector computational units. Also, it significantly reduces th...

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Bibliographic Details
Published inProceedings - International Symposium on High-Performance Computer Architecture pp. 481 - 492
Main Authors Aga, Shaizeen, Jeloka, Supreet, Subramaniyan, Arun, Narayanasamy, Satish, Blaauw, David, Das, Reetuparna
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2017
Subjects
Cache
Computer architecture
Data Movement
Energy
Geometry
In-Memory Processing
Program processors
Random access memory
Robustness
Throughput
Vector Processing
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Summary:This paper presents the Compute Cache architecture that enables in-place computation in caches. Compute Caches uses emerging bit-line SRAM circuit technology to re-purpose existing cache elements and transforms them into active very large vector computational units. Also, it significantly reduces the overheads in moving data between different levels in the cache hierarchy. Solutions to satisfy new constraints imposed by Compute Caches such as operand locality are discussed. Also discussed are simple solutions to problems in integrating them into a conventional cache hierarchy while preserving properties such as coherence, consistency, and reliability. Compute Caches increase performance by 1.9× and reduce energy by 2.4× for a suite of data-centric applications, including text and database query processing, cryptographic kernels, and in-memory checkpointing. Applications with larger fraction of Compute Cache operations could benefit even more, as our micro-benchmarks indicate (54× throughput, 9× dynamic energy savings).
ISSN:2378-203X
DOI:10.1109/HPCA.2017.21